Current trends in the semiconductor and electronics industry require memory devices to be made smaller, faster and require less power consumption. One reason for these trends is that more personal devices are being manufactured that are relatively small and portable, thereby relying on battery power. In addition to being smaller and more portable, personal devices are also requiring increased memory and more computational power and speed. In light of all these trends, there is an ever increasing demand in the industry for smaller, faster, and lower power dissipation memory cells and transistors used to provide the core functionality of these memory devices.
Semiconductor memories can, for example, be characterized as volatile random access memories (RAMs) or nonvolatile read only memories (ROMs), where RAMs can either be static (e.g. SRAM) or dynamic (e.g. DRAM), differing mainly in the manner by which they store a state of a bit. Several types of DRAM memory cells are used commonly, including a single capacitor memory cell (1T1C) and a dual capacitor memory cell (2T2C). As illustrated in FIG. 1A, conventional 1T1C DRAM cell 105 includes one access transistor 108 and one memory storage capacitor 110. A storage node capacitor plate (storage plate) 112 of the storage capacitor 110 is connected to a source terminal (source node) 114 of the transistor 108. The 1T1C cell 105 is read from, or written into by applying a signal via the word line WL 115 to the gate 116 of the transistor, thereby coupling the storage plate 112 of the capacitor 110 to the drain 117 of the transistor and the bit line BL 118. A ground node (ground plate) 120 of the storage capacitor 110 is connected to a common ground of the memory array. A sense amplifier (not shown) is connected to the bitline 118 and detects the voltage associated with a logic value of either 1 or 0 associated with the charge of the DRAM capacitor 110. In this manner, the memory cell data is retrieved.
Ferroelectric RAM (FeRAM or FRAM) is a type of non-volatile memory that uses a ferroelectric layer to achieve non-volatility. As shown in FIG. 1B, conventional FeRAM storage cell 10 is activated through the word-line (WL) 12, and written or read through the bit-line (BL) 14 and plate-line (PL) 16. As illustrated, the storage cell 10 includes a storage capacitor that can store a ferroelectric capacitance (CFE), to define a voltage differential Vc.
Magnetic random access memory (MRAM) is a type of non-volatile memory. FIG. 1C shows a schematic diagram of a portion 30 of a conventional MRAM array, which includes a plurality of memory cells 52-59. Each memory cell 52-59 includes a magnetoresistive (MR) element 20 27 and a transistor 30 37. The transistors 30 33 are coupled to each other via a word line (WL1) 40, and transistors 34 37 are coupled to each other via a word line (WL2) 41, where the word lines 40, 41 form the gate electrode for the transistors 30 37. The transistors 30 33 are also coupled to each other via a program line (PL1) 42, and transistors 34 37 are coupled via a program line (PL2) 43, where the program lines 42, 43 serve as virtual ground lines. Similarly, the MR elements 20 and 24 are coupled to each other by bit line (BL1) 45, MR elements 21 and 25 are coupled to each other by bit line (BL2) 46, MR elements 22 and 26 are coupled to each other by bit line (BL3) 47, and MR elements 23 and 27 are coupled to each other by bit line (BL4) 48.
The basic CMOS SRAM cell generally includes two n-type or n-channel (NMOS) pull-down or drive transistors and two p-type (PMOS) pull-up or load transistors in a cross-coupled inverter configuration, with two additional NMOS select or pass-gate transistors added to make up a standard double-sided or differential six-transistor memory cell (a DS 6T SRAM cell, a 6T SRAM cell, or simply a 6T cell). 8 transistor, 9 transistor, 5 transistor and 4 transistor SRAM cells are also known. Additionally, application specific SRAM cells can include an even greater number of transistors. A plurality of transistors are utilized in SRAM requiring matched electrical characteristics to provide predictable cell switching characteristics, reliable circuit performance, and minimize array power dissipation.
FIG. 1D is schematic of a conventional differential SRAM 6T cell 130. As illustrated, the SRAM cell 130 comprises a data storage cell or latch 132, generally including a pair of cross-coupled inverters, for example, inverter 142, and inverter 144, the latch 132 operable to store a data bit state. FIG. 1D illustrates that the bit is stored in the latch 132 at the data nodes or first and second latch nodes 134 and 136, respectively, having a high or “1” state and a low or “0” state, respectively. Cell 130 of FIG. 1D also comprises a pair of wordline pass transistors 146, 148 to read and write the data bit between the cross-coupled inverters 142, 144 and bitlines BL 160, BL-bar 162, when enabled by wordline 164.
Respective inverters 142, 144 comprise a p-type MOS (PMOS) pull-up or load transistor Q1 150, Q2 152 and an n-type (NMOS) pull-down transistor Q3 154, Q4 156. Pass gates (e.g., transistors) Q5 146, Q6 148 are n-channel as well, which generally supply higher conductance as compared to p-channel transistors. Pass transistors 146, 148 are enabled by wordline 164 and accessed by bitlines 160, 162 to set or reset the SRAM latch 130. FIG. 1D further illustrates that inverters 142, 144 of the SRAM memory cell 130 are connected together to a Vdd drain power supply line 170 and a Vss source power supply line 180. Both Vdd drain power supply line 170 and a Vss source power supply line 180 are generally provide at fixed voltage levels, such as 1.2 Volts and 0 Volts, respectively.
In general, SRAM cells are more stable and have better data retention where the respective pMOS (150, 152) and nMOS (154, 156) transistors are balanced and matched within the two inverters (142, 144). However, as dimensions are reduced to scale down devices, it becomes increasingly difficult to achieve a balance in the relative strengths of the pass gate, drive, and load transistors over the desired range of temperature, bias conditions, and process variations, as well as achieving matched transistor characteristics. As a result, SRAM cells formed as such can be adversely affected by varying operating characteristics and may be unstable and may not retain the desired bit state, during read or write operations.
During conventional read or write operations, bitlines 160 and 162 are initially precharged to a high or “1” state as illustrated. A read voltage is asserted to wordline WL 164 during a read or a write operation to activate (turn-on) pass transistors Q5 146 and Q6 148 into conduction, whereby latch 132 may be accessed by bitlines 160 and 162, respectively. With the prior data states as shown in FIG. 1D, an exemplary high state “1” is on a first latch node 134 at the gate of Q4 156, and a low state “0” is on a second latch node 136 at the gate of Q3 154. With these data states, only Q4 156 on the “low side” conducts via latch node 136, and pulls bitline-bar 162 lower, while Q3 154 on the “high side” does not conduct and thus, leaves bitline 160 high. Thus, given a finite amount of time, the cell will increasingly establish a greater differential voltage between the bitlines 160 and 162.
The intrinsic stability of a conventional SRAM cell is known to correspond to a noise-margin of a cross-coupled inverter loop of the cell when it is disconnected from the bit-lines, referred to commonly as the static noise margin (SNM). In contrast, the read stability of the cell corresponds to the noise-margin of the inverter loop with the word-line being active and the cell internal nodes being connected to the bit-lines. The read stability is usually worse than the intrinsic stability. As a result, the power supply can drop to a far lower value than when the cell is read-out. Vmin refers to the lowest power supply voltage at which an SRAM array still functions properly.
With scaling, it is increasingly difficult to design and operate an SRAM cell to be both stable and to be writeable across process variation, such as threshold variation, and across supply voltage variation. Supply voltage variation is often associated with use of a battery as the power supply source for the SRAM. Concurrently maintaining adequate read current (Iread) is also a problem.
For minimizing SRAM and other memory power consumption, as with other non-memory circuits, it is generally desirable for the total power supply voltage to be as low as possible. In the conventional case Vss is held at ground, Vdd needs to be minimized. Vdd for the array is generally referred to as VDDM. It is noted that VDDM is only set by the user within certain limits, since for most applications VDDM changes over time, such as a function of battery charge level as well as other factors that are known to affect VDDM. A low VDDM is known to degrade writeability and Iread. As noted above, process variation which can be significant even across a given die, can also be a factor in determining stability, writeability (Vtrip) and read current. What is needed is a memory circuit that is capable of compensating for process variation, such as threshold variation, in the case of SRAM and across supply voltage variation to relax the SNM/Vtrip/read current tradeoff to allow further scaling of SRAM cells.